M5M4V4265CTP-6S データシートの表示（PDF） - MITSUBISHI ELECTRIC
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M5M4V4265CTP-6S
MITSUBISHI ELECTRIC
M5M4V4265CTP-6S Datasheet PDF : 31 Pages
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MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and EDO Mode Cycles)
(Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted, see notes 14,15)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Min Max Min Max Min Max
tREF
Refresh cycle time
8.2
8.2
8.2
ms
tREF
Refresh cycle time *
tRP
RAS high pulse width
tRCD
Delay time, RAS low to CAS low
tCRP
Delay time, CAS high to RAS low
tRPC
Delay time, RAS high to CAS low
tCPN
CAS high pulse width
tRAD
Column address delay time from RAS low
128
128
128
ms
30
40
50
ns
(Note 16) 18
32
20
45 20
50
ns
5
5
5
ns
0
0
0
ns
8
10
10
ns
(Note 17) 13
25
15
30 15
35
ns
tASR
Row address setup time before RAS low
0
0
0
ns
tASC
Column address setup time before CAS low
(Note 18) 0
10
0
13
0
13
ns
tRAH
Row address hold time after RAS low
8
10
10
ns
tCAH
Column address hold time after CAS low
8
10
10
ns
tDZC
Delay time, data to CAS low
(Note 19) 0
0
0
ns
tDZO
Delay time, data to OE low
(Note 19) 0
0
0
ns
tRDD
Delay time, RAS high to data
(Note 20) 13
15
20
ns
tCDD
Delay time, CAS high to data
(Note 20) 13
15
20
ns
tODD
tT
Delay time, OE high to data
Transition time
(Note 20) 13
15
20
ns
(Note 21) 1
50
1
50
1
50
ns
Note 14 : The timing requirements are assumed tT=2ns.
Note 15 : VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Note 16 : tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Note 17 : tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA.
Note 18 : tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by tCAC.
Note 19 : Either tDZC or tDZO must be satisfied.
Note 20 : Either tRDD or tCDD or tODD must be satisfied.
Note 21 : tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC
Read cycle time
tRAS
RAS low pulse width
tCAS
CAS low pulse width
tCSH
CAS hold time after RAS low
tRSH
RAS hold time after CAS low
tRCS
Read setup time before CAS low
tRCH
Read hold time after CAS high
tRRH
Read hold time after RAS high
tRAL
Column address to RAS hold time
tCAL
Column address to CAS hold time
tORH
RAS hold time after OE low
tOCH
CAS hold time after OE low
Note 22 : Either tRCH or tRRH must be satisfied for a read cycle.
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Min Max Min Max Min Max
90
110
130
ns
50 10000 60 10000 70 10000
ns
8 10000 10 10000 13 10000
ns
40
48
55
ns
13
15
20
ns
0
0
0
ns
(Note 22)
0
0
0
ns
(Note 22)
0
0
0
ns
25
30
35
ns
13
18
23
ns
13
15
20
ns
13
15
20
ns
5
M5M4V4265CJ,TP-5,-5S:under development
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