M45PE80-VMN6TG データシートの表示（PDF） - Numonyx -> Micron

部品番号

コンポーネント説明

メーカー

M45PE80-VMN6TG

8 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability and a 50 MHz SPI bus interface

Numonyx -> Micron 

M45PE80

Instructions

6.5

Read Data Bytes (READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that

address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum

frequency fR, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 10.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)

instruction, while an Erase, Program or Write cycle is in progress, is rejected without having

any effects on the cycle that is in progress.

Figure 10. Read Data Bytes (READ) instruction sequence and data-out sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

C

Instruction

24-Bit Address

D

23 22 21

MSB

High Impedance

Q

1. Address bits A23 to A20 are Don’t Care.

3210

Data Out 1

Data Out 2

76543 2107

MSB

AI03748D

21/47

Share Link: