MT46V2M32V1LG-5 データシートの表示（PDF） - Micron Technology

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MT46V2M32V1LG-5

DOUBLE DATA RATE (DDR) SDRAM

Micron Technology 

FUNCTIONAL BLOCK DIAGRAM

2 Meg x 32

64Mb: x32

DDR SDRAM

CKE

CK#

CK

CS#

WE#

CAS#

RAS#

CONTROL

LOGIC

BANK3

BANK2

BANK1

MODE REGISTERS

13

A0-A10,

BA0, BA1

13

ADDRESS

REGISTER

REFRESH 11

COUNTER

ROW-

11

ADDRESS

MUX

11

BANK0

ROW-

ADDRESS

LATCH

&

DECODER

2048

BANK0

MEMORY

ARRAY

(2048 x 256 x 32)

SENSE AMPLIFIERS

2048

2

BANK

CONTROL

LOGIC

2

I/O GATING

DM MASK LOGIC

256

(x32)

COLUMN

DECODER

COLUMN-

ADDRESS

7

8

COUNTER/

LATCH

1

CA0

CK

32

64

READ

LATCH 32

MUX

DATA

DLL

32

DQS

GENERATOR

DRVRS

1

CA0

CA0

DQS

64

4

MASK

WRITE

4

64

FIFO

8

&

DRIVERS

32

64

clk

clk

32

out

in DATA

4

4

4

RCVRS

32

32

32

CK

INPUT

1

REGISTERS

DQ0 -

DQ31,

DM0 -

DM3

DQS

64Mb: x32 DDR SDRAM

2M32DDR-07.p65 – Rev. 12/01

4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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