
A(18:0)
E1
tAVET
tETEF
E2
or
tAVET
tETEF
E1
E2
W
tWLEF
D(7:0)
Q(7:0)
tWLQZ
APPLIED DATA
tDVEF
tEFDX
Assumptions & Notes:
1. G < VIL (max). (If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle).
2. Either E1 scenario above can occur.
tAVAV
tEFAX
tEFAX
Figure 4b. SRAM Write Cycle 2: Chip Enable - Controlled Access
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