M24C64-WMN3 データシートの表示（PDF） - STMicroelectronics

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M24C64-WMN3

64Kbit and 32Kbit Serial I²C Bus EEPROM

STMicroelectronics 

MEMORY ORGANIZATION

The memory is organized as shown in Figure 6..

Figure 6. Block Diagram

WC

E0

E1

E2

SCL

SDA

Control Logic

I/O Shift Register

High Voltage

Generator

Address Register

and Counter

Data

Register

M24C64, M24C32

1 Page

X Decoder

AI06899

7/26

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