
LTC2240-10
TIMING DIAGRAMS
LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
ANALOG
INPUT
ENC–
ENC+
D0-D9, OF
CLKOUT–
CLKOUT+
tAP
N
tH
N+1
tL
N+2
N+3
N+4
tD
N–5
tC
N–4
N–3
N–2
N–1
224010 TD01
ANALOG
INPUT
ENC–
ENC+
DA0-DA9, OFA
CLKOUTB
CLKOUTA
DB0-DB9, OFB
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
N
tH
N+1
tL
N+2
N+3
N+4
tD
N–5
tC
N–4
N–3
N–2
N–1
HIGH IMPEDANCE
224010 TD02
12
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