LTC1736C データシートの表示（PDF） - Linear Technology

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LTC1736C

5-Bit Adjustable High Efficiency Synchronous Step-Down Switching Regulator

Linear Technology 

LTC1736

APPLICATIO S I FOR ATIO

50A IPK RATING

VIN

12V

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

LTC1736

1736 F09

Figure 9. Plugging into the Cigarette Lighter

Design Example

As a design example, assume VIN = 12V(nominal), VIN =

22V(max), VOUT = 1.6V(nominal), 1.8V to 1.3V range, IMAX

= 12A and f = 275kHz. RSENSE and COSC can immediately

be calculated:

RSENSE = 50mV/12A = 0.0042Ω

COSC = 1.61(107)/(275kHz) – 11pF = 47pF

Assume a 1.2µH inductor and check the actual value of the

ripple current. The following equation is used :

∆IL

=

VOUT

(f)(L)



1–

VOUT

VIN





The highest value of the ripple current occurs at the

maximum input and output voltages:

∆IL

=

1.8V

275kHz(1.2µH)



1–

1.8V 

22V 

=

5A

The maximum ripple current is 42% of maximum output

current, which is about right.

Next, verify the minimum on-time of 200ns is not violated.

The minimum on-time occurs at maximum VIN and mini-

mum VOUT.

( ) tON(MIN) = VOUT

VIN(MAX) f

= 1.3V = 215ns

22V(275kHz)

The power dissipation on the topside MOSFET can be

easily estimated. Choosing a Fairchild FDS6612A results

in: RDS(ON) = 0.03Ω, CRSS = 80pF. At maximum input

voltage with T(estimated) = 50°C:

( ) [ ]( ) PMAIN

=

1.6 V

22V

2

12 1+ (0.005)(50°C – 25°C)

0.03Ω

( ) ( )( ) ( ) 2

+1.7 22V 12A 80pF 275kHz

= 571mW

Because the duty cycle of the bottom MOSFET is much

greater than the top, two larger MOSFETs must be paral-

leled. Choosing Fairchild FDS6680A MOSFETs yields a

parallel RDS(ON) of 0.0065Ω. The total power dissipaton

for both bottom MOSFETs, again assuming T = 50°C, is:

( ) ( )( ) PSYNC

=

22V – 1.6V

22V

12A

2

1.1

0.0065Ω

= 955mW

Thanks to current foldback, the bottom MOSFET dissipaton

in short circuit will be less than under full-load conditions.

CIN is chosen for an RMS current rating of at least 6A at

temperature. COUT is chosen with an ESR of 0.01Ω for low

output ripple. The output ripple in continuous mode will be

highest at the maximum input voltage. The output voltage

ripple due to ESR is approximately:

VORIPPLE = RESR(∆IL) = 0.01Ω(5A) = 50mVP-P

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1736. These items are also illustrated graphically in

the layout diagram of Figure 10. Check the following in

your layout:

1. Are the signal and power grounds segregated? The

LTC1736 PGND pin should tie to the GND plane close to

the input capacitor. The SGND pin should then connect

to PGND and all components that connect to SGND

should make a single point tie to the SGND pin. The low

side FET source pins should connect directly to the

input capacitor ground.

25

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