1418CG データシートの表示（PDF） - Linear Technology

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1418CG

Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O

Linear Technology 

LTC1418

APPLICATIONS INFORMATION

error adjustment is achieved by adjusting the offset applied

to the AIN– input. For zero offset error apply –125µV (i.e.,

–0.5LSB) at AIN+ and adjust the offset at the AIN– input

until the output code flickers between 0000 0000 0000

00 and 1111 1111 1111 11. For full-scale adjustment,

an input voltage of 2.047625V (FS – 1.5LSBs) is applied

to AIN+ and R2 is adjusted until the output code flickers

between 0111 1111 1111 10 and 0111 1111 1111 11.

BOARD LAYOUT AND GROUNDING

Wire wrap boards are not recommended for high reso-

lution or high speed A/D converters. To obtain the best

performance from the LTC1418, a printed circuit board

with ground plane is required. The ground plane under

the ADC area should be as free of breaks and holes as

possible, such that a low impedance path between all ADC

grounds and all ADC decoupling capacitors is provided.

It is critical to prevent digital noise from being coupled to

the analog input, reference or analog power supply lines.

Layout should ensure that digital and analog signal lines

are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track.

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

Pin 5 (AGND) and Pin 14 (DGND) and all other analog

grounds should be connected to this single analog ground

plane. The REFCOMP bypass capacitor and the VDD bypass

capacitor should also be connected to this analog ground

plane. No other digital grounds should be connected to this

analog ground plane. Low impedance analog and digital

power supply common returns are essential to low noise

operation of the ADC and the foil width for these tracks

should be as wide as possible. In applications where the

ADC data outputs and control signals are connected to

a continuously active microprocessor bus, it is possible

to get errors in the conversion results. These errors are

due to feedthrough from the microprocessor to the suc-

cessive approximation comparator. The problem can

be eliminated by forcing the microprocessor into a wait

state during conversion or by using three-state buffers to

isolate the ADC data bus. The traces connecting the pins

and bypass capacitors must be kept short and should be

made as wide as possible.

The LTC1418 has differential inputs to minimize noise

coupling. Common mode noise on the AIN+ and AIN– leads

will be rejected by the input CMRR. The AIN– input can be

used as a ground sense for the AIN+ input; the LTC1418

will hold and convert the difference voltage between AIN+

and AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should

be kept as short as possible. In applications where this is

not possible, the AIN+ and AIN– traces should be run side

by side to equalize coupling.

SUPPLY BYPASSING

High quality, low series resistance ceramic, 10µF bypass

capacitors should be used at the VDD and REFCOMP

pins. Surface mount ceramic capacitors such as Murata

GRM235Y5V106Z016 provide excellent bypassing in a

small board space. Alternatively 10µF tantalum capacitors

in parallel with 0.1µF ceramic capacitors can be used.

1 AIN+

LTC1418

ANALOG

INPUT

+–

CIRCUITRY

AIN– VREF

2

3

REFCOMP AGND

4

5

1μF

10μF

VSS

27

10μF

VDD

28

DGND

14

10μF

ANALOG GROUND PLANE

1418 F11

Figure 11. Power Supply Grounding Practice

DIGITAL

SYSTEM

For more information www.linear.com/LTC1418

1418fa

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