LM3S2110-IRN50 データシートの表示（PDF） - Unspecified
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LM3S2110-IRN50 Datasheet PDF : 485 Pages
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LM3S2110 Microcontroller
Table of Contents
About This Document .................................................................................................................... 18
Audience .............................................................................................................................................. 18
About This Manual ................................................................................................................................ 18
Related Documents ............................................................................................................................... 18
Documentation Conventions .................................................................................................................. 18
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 20
Product Features ...................................................................................................................... 20
Target Applications .................................................................................................................... 25
High-Level Block Diagram ......................................................................................................... 26
Functional Overview .................................................................................................................. 27
ARM Cortex™-M3 ..................................................................................................................... 27
Motor Control Peripherals .......................................................................................................... 27
Analog Peripherals .................................................................................................................... 28
Serial Communications Peripherals ............................................................................................ 28
System Peripherals ................................................................................................................... 30
Memory Peripherals .................................................................................................................. 31
Additional Features ................................................................................................................... 31
Hardware Details ...................................................................................................................... 32
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 33
Block Diagram .......................................................................................................................... 34
Functional Description ............................................................................................................... 34
Serial Wire and JTAG Debug ..................................................................................................... 34
Embedded Trace Macrocell (ETM) ............................................................................................. 35
Trace Port Interface Unit (TPIU) ................................................................................................. 35
ROM Table ............................................................................................................................... 35
Memory Protection Unit (MPU) ................................................................................................... 35
Nested Vectored Interrupt Controller (NVIC) ................................................................................ 35
3
Memory Map ....................................................................................................................... 39
4
Interrupts ............................................................................................................................ 41
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
JTAG Interface .................................................................................................................... 43
Block Diagram .......................................................................................................................... 44
Functional Description ............................................................................................................... 44
JTAG Interface Pins .................................................................................................................. 45
JTAG TAP Controller ................................................................................................................. 46
Shift Registers .......................................................................................................................... 47
Operational Considerations ........................................................................................................ 47
Initialization and Configuration ................................................................................................... 50
Register Descriptions ................................................................................................................ 50
Instruction Register (IR) ............................................................................................................. 50
Data Registers .......................................................................................................................... 52
6
6.1
6.1.1
6.1.2
System Control ................................................................................................................... 54
Functional Description ............................................................................................................... 54
Device Identification .................................................................................................................. 54
Reset Control ............................................................................................................................ 54
November 29, 2007
3
Preliminary
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