ISL95870BHRZ-T データシートの表示（PDF） - Intersil
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ISL95870BHRZ-T Datasheet PDF : 29 Pages
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ISL95870, ISL95870A, ISL95870B
Theory of Operation
The following sections will provide a detailed description
of the inner workings of the ISL95870, ISL95870A,
ISL95870B.
Power-On Reset
The IC is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR)
threshold voltage VVCC_THR. The controller will become
disabled when the voltage at the VCC pin decreases
below the falling POR threshold voltage VVCC_THF. The
POR detector has a noise filter of approximately 1µs.
Start-Up Timing
Once VCC has ramped above VVCC_THR, the controller
can be enabled by pulling the EN pin voltage above the
input-high threshold VENTHR. Approximately 20µs later,
the voltage at the SREF pin begins slewing to the
designated VID set-point. The converter output voltage
at the FB feedback pin follows the voltage at the SREF
pin. During soft-start, The regulator always operates in
CCM until the soft-start sequence is complete.
Start-Up and Voltage-Step Operation for
ISL95870
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage VVCC_THR, and the voltage
on the EN pin has increased above the rising enable
threshold voltage VENTHR, the SREF pin releases its
discharge clamp, and enables the reference amplifier
VSET. The soft-start current ISS is limited to 17µA and is
sourced out of the SREF pin and charges capacitor CSOFT
until VSREF equals VREF. The regulator controls the PWM
such that the voltage on the FB pin tracks the rising
voltage on the SREF pin. The elapsed time from when the
EN pin is asserted to when VSREF has charged CSOFT to
VREF is called the soft-start delay tSS which is given by
Equation 1:
tSS
=
V-----S----R----E----F----⋅---C-----S----O----F----T--
ISS
(EQ. 1)
Where:
- ISS is the soft-start current source at the 17µA
limit
- VSREF is the buffered VREF reference voltage
The end of soft-start is detected by ISS tapering off when
capacitor CSOFT charges to VREF. The internal SSOK flag
is set, the PGOOD pin goes high, and diode emulation
mode (DEM) is enabled.
Choosing the CSOFT capacitor to meet the requirements
of a particular soft-start delay tSS is calculated using
Equation 2, which is written as follows:
CSOFT
=
t--S----S-----⋅---I--S----S--
VSREF
(EQ. 2)
Where:
- tSS is the soft-start delay
- ISS is the soft-start current source at the 17µA
limit
- VSREF is the buffered VREF reference voltage
Start-Up and Voltage-Step Operation for
ISL95870A, ISL95870B
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage VVCC_THR, and the voltage
on the EN pin has increased above the rising enable
threshold voltage VENTHR, the SREF pin releases its
discharge clamp and enables the reference amplifier
VSET. The soft-start current ISS is limited to 17µA and is
sourced out of the SREF pin into the parallel RC network
of capacitor CSOFT and resistance RT. The resistance RT
is the sum of all the series connected RSET programming
resistors and is written as Equation 3:
RT = RSET1 + RSET2 + …RSET(n)
(EQ. 3)
The voltage on the SREF pin rises as ISS charges CSOFT
to the voltage reference setpoint selected by the state of
the VID inputs at the time the EN pin is asserted. The
regulator controls the PWM such that the voltage on the
FB pin tracks the rising voltage on the SREF pin. Once
CSOFT charges to the selected setpoint voltage, the ISS
current source comes out of the 17µA current limit and
decays to the static value set by VSREF/RT. The elapsed
time from when the EN pin is asserted to when VSREF
has reached the voltage reference setpoint is the
soft-start delay tSS which is given by Equation 4:
tSS = – (RT ⋅ CSOFT) ⋅ LN(1 – -V----SI--S-T---SA----R-⋅---TR-----T-U---P-- )
(EQ. 4)
Where:
- ISS is the soft-start current source at the 17µA
limit
- VSTART-UP is the setpoint reference voltage
selected by the state of the VID inputs at the time
EN is asserted
- RT is the sum of the RSET programming resistors
The end of soft-start is detected by ISS tapering off when
capacitor CSOFT charges to the designated VSET voltage
reference setpoint. The SSOK flag is set, and the PGOOD
pin goes high.
The ISS current source changes over to the voltage-step
current source IVS which has a current limit of ±85µA.
Whenever the VID inputs or the external setpoint
reference programs a different setpoint reference
voltage, the IVS current source charges or discharges
capacitor CSOFT to that new level at ±85µA. Once CSOFT
charges to the selected setpoint voltage, the IVS current
source comes out of the 85µA current limit and decays to
the static value set by VSREF/RT. The elapsed time to
charge CSOFT to the new voltage is called the voltage-
step delay tVS and is given by Equation 5:
tVS = – (RT ⋅ CSOFT) ⋅ LN(1 – (---V----N----E-I--V-W---S----–-⋅---RV----TO-----L---D-----))
(EQ. 5)
15
FN6899.0
December 22, 2009
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