IS61LV12824 データシートの表示（PDF） - Integrated Silicon Solution

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IS61LV12824

128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

Integrated Silicon Solution 

IS61LV12824

ISSI ®

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

Symbol Parameter

-8

-10

Min. Max.

Min. Max.

Unit

tRC

Read Cycle Time

8—

10 —

ns

tAA

Address Access Time

—8

— 10

ns

tOHA

Output Hold Time

3—

3—

ns

tACE

CE1, CE2 Access Time

8—

— 10

ns

tACE2

CE2 Access Time

tDOE

OE Access Time

—4

—4

ns

tHZOE(2)

OE to High-Z Output

03

03

ns

tLZOE(2)

OE to Low-Z Output

0—

0—

ns

tHZCE(2)

CE1, CE2 to High-Z Output

04

05

ns

tHZCE2(2) CE2 to High-Z Output

tLZCE(2)

CE, CE2 to Low-Z Output

3—

3—

ns

tLZCE2(2)

CE2 to Low-Z Output

Notes:

1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

06/22/05

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