IDT82V3385EQG データシートの表示（PDF） - Integrated Device Technology
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IDT82V3385EQG Datasheet PDF : 145 Pages
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IDT82V3385
SYNCHRONOUS ETHERNET WAN PLL
Input Clock INn
(1 < n < 5)
Pre-Divider
IN3_DIV[1:0] bits / IN4_DIV[1:0] bits
HF Divider
(for IN3 & IN4 only) 1
0
Lock 8k Divider
DivN Divider
2=<N=<19440
LOCK_8K bit
DIRECT_DIV bit
00
10 DPLL clock
01
Figure 3. Pre-Divider for An Input Clock
Table 4: Pre-Divider Function
Pre-Divider
HF- Divider
Divider Bypassed
Lock 8K Divider
Input Clock INn frequency
>155.52 MHz
2 kHz, 4 kHz, 8 kHz, 1.544 MHz, 2.048
MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz or
38.88 MHz
1.544 MHz, 2.048 MHz, 6.48 MHz, 19.44
MHz, 25.92 MHz or 38.88 MHz
Control Register
IN3_DIV[1:0]
IN4_DIV[1:0]
IN_FREQ[3:0] – set to match input Clock INn frequency.
LOCK_8K= 0’b; DIRECT_DIV= 0’b (Bypass Dividers)
IN_FREQ[3:0] – set to match input Clock INn frequency.
LOCK_8K= 1’b; DIRECT_DIV= 0’b (select Lock 8k Divider)
LOCK_8K= 0’b; DIRECT_DIV= 1’b (select DivN Divider)
Register/ Address1
IN3_IN4_HF_DIV_CNFG (18)
IN1_CNFG ~ IN5_CNFG
(16 ~ 17, 19 ~ 1A, 1F)
IN1_CNFG ~ IN5_CNFG
(16 ~ 17, 19 ~ 1A, 1F)
Nx8kHz
(2 N 19440)
DivN
Example:
5 MHz = 625 x 8kHz
25 MHz = 3125 x 8kHz
Note 1: Please see register description for details.
IN_FREQ[3:0] – set to the DPLL required frequency.
(‘0000’: 8 kHz (default))
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[14:0]
Example:
25 MHz = 3125 x 8kHz
Division Factor = 3125 -1= 3124 Dec (or 0C34h)
PRE_DIVN_VALUE[7:0]= 34h
PRE_DIVN_VALUE[14:8]= 0Ch
IN1_CNFG ~ IN5_CNFG
(16 ~ 17, 19 ~ 1A, 1F)
PRE_DIV_CH_CNFG (23)
PRE_DIVN[14:8]_CNFG (25),
PRE_DIVN[7:0]_CNFG (24)
Functional Description
20
May 14, 2010
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