IDT82V3380EQG データシートの表示（PDF） - Integrated Device Technology
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IDT82V3380EQG Datasheet PDF : 175 Pages
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IDT82V3380
SYNCHRONOUS ETHERNET WAN PLL
3.7.3 PHASE LOCK ALARM (T0 ONLY)
A phase lock alarm will be raised when the selected input clock can
not be locked in T0 DPLL within a certain period. This period can be cal-
culated as follows:
Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]
The phase lock alarm is indicated by the corresponding
INn_PH_LOCK_ALARM bit (14 ≥ n ≥ 1).
The phase lock alarm can be cleared by the following two ways, as
selected by the PH_ALARM_TIMEOUT bit:
• Be cleared when a ‘1’ is written to the corresponding
INn_PH_LOCK_ALARM bit;
• Be cleared after the period (= TIME_OUT_VALUE[5:0] X
MULTI_FACTOR[1:0] in second) which starts from when the
alarm is raised.
The selected input clock with a phase lock alarm is disqualified for T0
DPLL locking.
Note that no phase lock alarm is raised if the T4 selected input clock
can not be locked.
Table 12: Related Bit / Register in Chapter 3.7
Bit
Register
FAST_LOS_SW
PH_LOS_FINE_LIMT[2:0]
PHASE_LOSS_FINE_LIMIT_CNFG
FINE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
WIDE_EN
PH_LOS_COARSE_LIMT[3:0]
PHASE_LOSS_COARSE_LIMIT_CNFG
COARSE_PH_LOS_LIMT_EN
T0_DPLL_SOFT_FREQ_ALARM
T4_DPLL_SOFT_FREQ_ALARM
T0_DPLL_LOCK
OPERATING_STS
T4_DPLL_LOCK
DPLL_FREQ_SOFT_LIMT[6:0]
FREQ_LIMT_PH_LOS
DPLL_FREQ_SOFT_LIMIT_CNFG
DPLL_FREQ_HARD_LIMT[15:0]
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG,
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG
T4_STS 1
INTERRUPTS3_STS
T4_STS 2
INTERRUPTS3_ENABLE_CNFG
TIME_OUT_VALUE[5:0]
MULTI_FACTOR[1:0]
PHASE_ALARM_TIME_OUT_CNFG
INn_PH_LOCK_ALARM (14 ≥ n ≥ 1)
IN1_IN2_STS ~ IN13_IN14_STS
PH_ALARM_TIMEOUT
INPUT_MODE_CNFG
T4_T0_SEL
T4_T0_REG_SEL_CNFG
Note: * The setting in the 5A and 5B registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Address (Hex)
5B *
5A *
52
65
67, 66
0F
12
08
43 ~ 49
09
07
Functional Description
28
May 19, 2009
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