IDT72V3673(2016) データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

メーカー

IDT72V3673
(Rev.:2016)

3.3 VOLT CMOS SyncFIFO™ WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

CLKB

CSB

W/RB

MBB

ENB

B0-B35

tENS1

tENS1

tENS2

tENS2

tDS

W1

tENH

tENH

tENH

tENH

tDH

COMMERCIAL TEMPERATURE RANGE

CLKA

MBF2

tPMF

tPMF

CSA

W/RA

MBA

tENS2

tENH

ENA

tEN

tPMR

tMDV

tDIS

A0-A35

FIFO Output Register

W1 (Remains valid in Mail2 Register after read)

4662 drw20

NOTE:

1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data (A18-A35 will

be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don't care inputs). In this second case, A0-A8 will have valid

data (A9-A35 will be indeterminate).

Figure 18. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)

26

Share Link: