IDT72V3673(2016) データシートの表示（PDF） - Integrated Device Technology

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IDT72V3673
(Rev.:2016)

3.3 VOLT CMOS SyncFIFO™ WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

CLKB

tCLK

tCLKH

tCLKL

CSB LOW

W/RB HIGH

MBB LOW

ENB

tENS2

tENH

COMMERCIAL TEMPERATURE RANGE

EF HIGH

tA

B0-B35

Previous Word in FIFO Output Register

tSKEW1(1)

CLKA

FF FIFO Full

CSA LOW

tCLK

tCLKH

tCLKL

1

Next Word From FIFO

2

t WFF

t WFF

W/RA HIGH

tENS2

tENH

MBA

tENS2

tENH

ENA

tDS

tDH

A0-A35

To FIFO

4662 drw16

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW1, then FF may transition HIGH one CLKA cycle later than shown.

2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.

Figure 14. FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)

CLKA

ENA

CLKB

AE

tENS2

tENH

tSKEW2 (1)

1

X Words in FIFO

2

tPAE

(X+1) Words in FIFO

tENS2

tPAE

tENH

ENB

4662 drw 17

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.

2. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.

3. If Port B size is word or byte, AE is set LOW by the last word or byte read from the FIFO, respectively.

Figure 15. Timing for AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).

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