IDT72205LB10PFG8(2017) データシートの表示（PDF） - Integrated Device Technology

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IDT72205LB10PFG8
(Rev.:2017)

CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

WCLK

tDS

D0 - D17

tENS

DATA WRITE 1

tENH

tDS

tENS

RCLK

tSKEW2

tFRL (1)

tREF

tREF

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DATA WRITE 2

tENH

tSKEW2

tFRL (1)

tREF

LOW

tA

Q0 - Q17

DATA IN OUTPUT REGISTER

DATA READ

2766 drw 11

NOTE:

1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2.

The Latency Timing applies only at the Empty Boundary (EF = LOW).

Figure 9. Empty Flag Timing

tCLK

tCLKH

tCLKL

WCLK

LD

tENS

tENH

tENS

WEN

D0–D15

tDS

PAE OFFSET

tDH

PAE OFFSET

PAF OFFSET

D0–D11

Figure 10. Write Programmable Registers

2766 drw 12

tCLKH

RCLK

tCLK

tCLKL

tENS

tENH

tENS

Q0–Q15

tA

UNKNOWN

PAE OFFSET

PAF OFFSET

Figure 11. Read Programmable Registers

11

PAE OFFSET

2766 drw 13

MARCH 2013

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