ICS8523I-03 データシートの表示（PDF） - Integrated Circuit Systems

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ICS8523I-03

LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Source

Q0:Q3

nQ0:nQ3

0

0

CLK0, nCLK0

Disabled; LOW

Disabled; HIGH

0

1

CLK1, nCLK1

Disabled; LOW

Disabled; HIGH

1

0

CLK0, nCLK0

Enabled

Enabled

1

1

CLK1, nCLK1

Enabled

Enabled

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge

as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK0 , nCLK0 and CLK1, nCLK1 inputs as described

in Table 3B.

nCLK0, nCLK1

CLK0, CLK1

Disabled

Enabled

CLK_EN

nQ0:nQ3

Q0:Q3

FIGURE 1. CLK_EN TIMING DIAGRAM

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

CLK0 or CLK1 nCLK0 or nCLK1

Outputs

Q0:Q3

nQ0:nQ3

Input to Output Mode

Polarity

0

0

LOW

HIGH

Differential to Differential

Non Inverting

1

1

HIGH

LOW

Differential to Differential

Non Inverting

0

Biased; NOTE 1

LOW

HIGH

Single Ended to Differential Non Inverting

1

Biased; NOTE 1

HIGH

LOW

Single Ended to Differential Non Inverting

Biased; NOTE 1

0

HIGH

LOW

Single Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single Ended to Differential

Inverting

NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".

8523AGI-03

www.icst.com/products/hiperclocks.html

3

REV. A OCTOBER 5, 2004

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