HV6810PJ-G(2013) データシートの表示（PDF） - Supertex Inc
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HV6810PJ-G Datasheet PDF : 9 Pages
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Pin Description
20-Lead SOW (WG)
Pin #
Function
1
Q8
2
Q7
3
Q6
4
CLOCK
5
VSS
6
N/C
7
VDD
8
LE (STROBE)
9
Q5
10
Q4
11
Q3
12
Q2
13
Q1
14
BLANKING
15
DATA IN
16
VBB
17
SERIAL DATA OUT
18
N/C
19
Q10
20
Q9
HV6810
Description
High voltage output.
Input data are shifted into the data shift register on the positive edge of the clock.
Usually VSS = 0V, ground connection.
No connection.
Low voltage power supply.
When LE is high, the shift register output is latched to Q output. When LE stays high,
the latches are in transparent mode.
High voltage output.
When blanking is high, all Q’s are forced to a low state, regardless of data in each
channel.
Input data for the input shift register.
High voltage power supply.
Output data from the shift register.
No connection.
High voltage output.
Doc.# DSFP-HV6810
E070913
Supertex inc.
7
www.supertex.com
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