AD14060L(RevB) データシートの表示（PDF） - Analog Devices
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AD14060L Datasheet PDF : 48 Pages
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AD14060/AD14060L
MEMORY READ—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 8. Specifications
Parameter
Timing Requirements:
tDAD
Address, Delay to Data Valid1, 2
tDRLD
RD Low to Data Valid1
tHDA
tHDRH
Data Hold from Address3
Data Hold from RD High3
tDAAK
tDSAK
ACK Delay from Address2, 4
ACK Delay from RD Low4
Switching Characteristics:
tDRHA
Address Hold after RD High
tDARL
Address to RD Low2
tRW
RD Pulse Width
tRWR
RD High to WR, RD, DMAGx Low
tSADADC Address Setup before ADRCLK High2
5V
3.3 V
Min
Max
Min
Max
Unit
17.5 + DT + W
17.5 + DT + W
ns
11.5 + 5 DT/8 + W
11.5 + 5 DT/8 + W ns
1
1
ns
2.5
2.5
ns
13.5 + 7 DT/8 + W
13.5 + 7 DT/8 + W ns
7.5 + DT/2 + W
7.5 + DT/2 + W ns
−0.5 + H
−0.5 + H
ns
1.5 + 3 DT/8
1.5 + 3 DT/8
ns
12.5 + 5 DT/8 + W
12.5 + 5 DT/8 + W
ns
8 + 3 DT/8 + HI
8 + 3 DT/8 + HI
ns
−0.5 + DT/4
−0.5 + DT/4
ns
W = number of wait states specified in WAIT register × tCK.
HI = tCK, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.
H = tCK, if an address hold cycle occurs as specified in WAIT register; otherwise, H = 0.
1 Data delay/setup: User must meet tDAD, tDRLD, or synchronous specification, tSSDATI.
2 For MSx, SW, BMS, the falling edge is referenced.
3 Data hold: User must meet tHDA, tHDRH, or synchronous specification, tHDATI. See the System Hold Time Calculation Example section for the calculation of hold times given
capacitive and dc loads.
4 ACK delay/setup: User must meet tDSAK, tDAAK, or synchronous specification, tSACKC.
ADDRESS
MSx, SW
BMS
RD
DATA
ACK
tDARL
tRW
tDAD
tDRLD
tDAAK
tDSAK
tDRHA
tHDA
tHDRH
tRWR
WR, DMAG
ADRCLK
(OUT)
tSADADC
Figure 7. Memory Read—Bus Master
Rev. B | Page 8 of 48
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