HMN1M8DN-120 データシートの表示（PDF） - Hanbit Electronics Co.,Ltd

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HMN1M8DN-120

Non-Volatile SRAM MODULE 8Mbit (1,024K X 8-Bit), 40Pin-DIP, 5V

Hanbit Electronics Co.,Ltd 

HANBit

- WRITE CYCLE NO.2 (/CE-Controlled)*1,2,3,4,5

HMN1M8DN

Address

tAW

tAS

tCW

tWR2

/CE

tWP

/WE

tDW

tDH2

DIN

Data-in

tWZ

DOUT

Data Undefined

High-Z

NOTE: 1. /CE or /WE must be high during address transition.

2. Because I/O may be active (/OE low) during this period, data input signals of opposite

polarity to the outputs must not be applied.

3. If /OE is high, the I/O pins remain in a state of high impedance.

4. Either tWR1 or tWR2 must be met.

5. Either tDH1 or tDH2 must be met.

- POWER-DOWN/POWER-UP TIMING

VCC

4.75

tPF

VPFD

4.25

VSO

VPFD

VSO

tFS

tWPT

tDR

tPU

tCER

/CE

PACKAGE DIMENSION

URL : www.hbe.co.kr

8

REV. 0.2 (August, 2002)

HANBit Electronics Co.,Ltd.

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