LT1578/LT1578-2.5
APPLICATIONS INFORMATION
How Do I Test Loop Stability?
The “standard” compensation for LT1578 is a 100pF
capacitor for CC, with RC = 0. While this compensation will
work for most applications, the “optimum” value for loop
compensation components depends, to various extents,
on parameters which are not well controlled. These in-
clude inductor value (±30% due to production tolerance,
load current and ripple current variations), output capaci-
tance (±20% to ±50% due to production tolerance,
temperature, aging and changes at the load), output
capacitor ESR (±200% due to production tolerance,
temperature and aging), and finally, DC input voltage and
output load current . This makes it important for the
designer to check out the final design to ensure that it is
“robust” and tolerant of all these variations.
One way to check switching regulator loop stability is by
pulse loading the regulator output while observing the
transient response at the output, using the circuit shown
in Figure 13. The regulator loop is “hit” with a small
transient AC load current at a relatively low frequency,
50Hz to 1kHz. This causes the output to jump a few
millivolts, then settle back to the original value, as shown
in Figure 14. A well behaved loop will settle back cleanly,
whereas a loop with poor phase or gain margin will “ring”
as it settles. The number of rings indicates the degree of
stability, and the frequency of the ringing shows the
approximate unity-gain frequency of the loop. Amplitude
of the signal is not particularly important, as long as the
amplitude is not so high that the loop behaves nonlinearly.
ADJUSTABLE
INPUT SUPPLY
SWITCHING
REGULATOR
ADJUSTABLE
DC LOAD
+
100µF TO
1000µF
RIPPLE FILTER
470Ω 4.7k
3300pF
330pF
50Ω
TO
OSCILLOSCOPE
SYNC
100Hz TO 1kHz
100mV TO 1VP-P
TO X1
OSCILLOSCOPE
PROBE
1578 F13
Figure 13. Loop Stability Test Circuit
10mV/DIV
5A/DIV
0.2ms/DIV
VOUT AT
IOUT = 500mA
BEFORE FILTER
VOUT AT
IOUT = 500mA
AFTER FILTER
VOUT AT
IOUT = 50mA
AFTER FILTER
LOAD PULSE
THROUGH 50Ω
f ≈ 780Hz
1578 F14
Figure 14. Loop Stability Check
22