HD64F3029X25W データシートの表示（PDF） - Renesas Electronics

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HD64F3029X25W

16-Bit Single-Chip Microcomputer

Renesas Electronics 

7.1.4 Input/Output Pins................................................................................................. 200

7.1.5 Register Configuration......................................................................................... 200

7.2 Register Descriptions (1) (Short Address Mode) .............................................................. 202

7.2.1 Memory Address Registers (MAR) ..................................................................... 202

7.2.2 I/O Address Registers (IOAR) ............................................................................. 203

7.2.3 Execute Transfer Count Registers (ETCR).......................................................... 203

7.2.4 Data Transfer Control Registers (DTCR) ............................................................ 205

7.3 Register Descriptions (2) (Full Address Mode) ................................................................ 208

7.3.1 Memory Address Registers (MAR) ..................................................................... 208

7.3.2 I/O Address Registers (IOAR) ............................................................................. 208

7.3.3 Execute Transfer Count Registers (ETCR).......................................................... 209

7.3.4 Data Transfer Control Registers (DTCR) ............................................................ 211

7.4 Operation .......................................................................................................................... 217

7.4.1 Overview.............................................................................................................. 217

7.4.2 I/O Mode.............................................................................................................. 219

7.4.3 Idle Mode............................................................................................................. 221

7.4.4 Repeat Mode ........................................................................................................ 224

7.4.5 Normal Mode....................................................................................................... 227

7.4.6 Block Transfer Mode ........................................................................................... 230

7.4.7 DMAC Activation................................................................................................ 235

7.4.8 DMAC Bus Cycle ................................................................................................ 237

7.4.9 Multiple-Channel Operation ................................................................................ 243

7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 244

7.4.11 NMI Interrupts and DMAC ................................................................................. 245

7.4.12 Aborting a DMAC Transfer................................................................................. 246

7.4.13 Exiting Full Address Mode.................................................................................. 247

7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 248

7.5 Interrupts........................................................................................................................... 249

7.6 Usage Notes ...................................................................................................................... 250

7.6.1 Note on Word Data Transfer................................................................................ 250

7.6.2 DMAC Self-Access.............................................................................................. 250

7.6.3 Longword Access to Memory Address Registers ................................................ 250

7.6.4 Note on Full Address Mode Setup....................................................................... 250

7.6.5 Note on Activating DMAC by Internal Interrupts ............................................... 251

7.6.6 NMI Interrupts and Block Transfer Mode ........................................................... 252

7.6.7 Memory and I/O Address Register Values .......................................................... 252

7.6.8 Bus Cycle when Transfer is Aborted ................................................................... 253

7.6.9 Transfer Requests by A/D Converter................................................................... 253

Section 8 I/O Ports .............................................................................................255

8.1 Overview........................................................................................................................... 255

8.2 Port 1................................................................................................................................. 258

8.2.1 Overview.............................................................................................................. 258

Rev. 2.0, 06/04, page xv of xxiv

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