GS832018GT-133IV データシートの表示（PDF） - Giga Semiconductor

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GS832018GT-133IV

2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

Giga Semiconductor 

GS832018/32/36T-xxxV

Mode Pin Functions

Mode Name

Pin Name State

Function

Burst Order Control

L

LBO

H

Linear Burst

Interleaved Burst

Output Register Control

L

FT

H or NC

Flow Through

Pipeline

Power Down Control

L or NC

ZZ

H

Active

Standby, IDD = ISB

Note:

There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the

above table.

There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in

the default states as specified in the above table.

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

00

01

10

11

2nd address

01

10

11

00

3rd address

10

11

00

01

4th address

11

00

01

10

Note:

The burst counter wraps to initial state on the 5th clock.

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

00

01

10

11

2nd address

01

00

11

10

3rd address

10

11

00

01

4th address

11

10

01

00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.04a 12/2007

7/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2003, GSI Technology

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