GS1560A データシートの表示（PDF） - Gennum -> Semtech
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GS1560A Datasheet PDF : 79 Pages
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
70
71
72
73, 74
Name
RC_BYP
RSV
MASTER/SLAVE
LOCKED
VCO, VCO
Timing
Type Description
Non
Synchronous
Input
/Outpu
t
GS1560A
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and
will be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The RC_BYP signal will be HIGH only when the device has successfully
locked to a SMPTE compliant input data stream. In this case, the serial
digital loop-through output will be a reclocked version of the input.
The RC_BYP signal will be LOW whenever the input does not conform
to a SMPTE compliant data stream. In this case, the serial digital
loop-through output will be a buffered version of the input.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH, the serial digital output will be a reclocked version of
the input signal regardless of whether the device is in SMPTE, DVB-ASI
or Data-Through mode.
When set LOW, the serial digital output will be a buffered version of
the input signal in all modes.
–
–
GS1561
Connect to CORE_VDD through 2.2kΩ.
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to determine the input / output selection for the DVB_ASI,
SD/HD, RC_BYP and SMPTE_BYPASS pins.
When set HIGH, the GS1560A is set to operate in master mode where
SD/HD, RC_BYP (GS1560A only) and SMPTE_BYPASS become status
signal output pins set by the device. In this mode, the GS1560A will
automatically detect, reclock, deserialize and process SD SMPTE and
HD SMPTE input data.
When set LOW, the GS1560A is set to operate in slave mode where
DVB_ASI, SD/HD, RC_BYP (GS1560A only) and SMPTE_BYPASS become
control signal input pins. In this mode, the application layer must set
these external device pins for the correct reception of either SMPTE or
DVB-ASI data. Slave mode also supports the reclocking and
deserializing of data not conforming to SMPTE or DVB-ASI streams.
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode.
It will be LOW otherwise.
Analog
Input
Differential inputs for the external VCO reference signal. For single
ended devices such as the GO1555/GO1525*, VCO should be AC
coupled to VCO_GND.
VCO is nominally 1.485GHz.
*For new designs use GO1555
GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer
Data Sheet
27360 - 12
June 2009
17 of 79
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