GS1560A データシートの表示（PDF） - Gennum -> Semtech
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GS1560A Datasheet PDF : 79 Pages
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
31
32
33, 68
34
35
36
Name
DATA_ERROR
FIFO_LD
CORE_GND
F
V
H
Timing
Type Description
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
The DATA_ERROR signal will be LOW when an error within the
received data stream has been detected by the device. This pin is a
logical 'OR'ing of all detectable errors listed in the internal
ERROR_STATUS register.
Once an error is detected, DATA_ERROR will remain LOW until the
start of the next video frame / field, or until the ERROR_STATUS
register is read via the host interface.
The DATA_ERROR signal will be HIGH when the received data stream
has been detected without error.
NOTE: It is possible to program which error conditions are monitored
by the device by setting appropriate bits of the ERROR_MASK register
HIGH. All error conditions are detected by default.
Synchronous
with PCLK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used as a control signal for external FIFO(s).
Normally HIGH but will go LOW for one PCLK period at SAV.
–
Power Ground connection for the digital core logic. Connect to digital GND.
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal.
The F signal will be HIGH for the entire period of field 2 as indicated
by the F bit in the received TRS signals.
The F signal will be LOW for all lines in field 1 and for all lines in
progressive scan systems.
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking.
The V signal will be HIGH for the entire vertical blanking period as
indicated by the V bit in the received TRS signals.
The V signal will be LOW for all lines outside of the vertical blanking
interval.
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video
data. H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register accessible via the host interface.
Active Line Blanking (H_CONFIG = 0h)
The H signal will be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1h)
The H signal will be HIGH for the entire horizontal blanking period as
indicated by the H bit in the received TRS ID words, and LOW
otherwise.
GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer
Data Sheet
27360 - 12
June 2009
13 of 79
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