DS2431X データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS2431X Datasheet PDF : 23 Pages
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DS2431: 1024-Bit, 1-Wire EEPROM
PARAMETER
I/O PIN, 1-Wire WRITE
Write-0 Low Time (Note 1)
Write-1 Low Time
(Notes 1, 15)
I/O PIN, 1-Wire READ
Read Low Time
(Notes 1, 16)
Read Sample Time
(Notes 1, 16)
EEPROM
Programming Current
Programming Time
Write/Erase Cycles
(Endurance)
Data Retention
SYMBOL
CONDITIONS
tW0L
Standard speed
Overdrive speed (Note 13)
Standard speed
tW1L
Overdrive speed
Standard speed
tRL
Overdrive speed
tMSR
Standard speed
Overdrive speed
IPROG
tPROG
NCY
tDR
(Note 17)
(Note 18)
At 25°C
At 85°C (worst case)
At 85°C (worst case)
MIN
60
7
5
1
5
1
tRL + δ
tRL + δ
200k
50k
10
TYP
MAX
120
16
15 - ε
2-ε
15 - δ
2-δ
15
2
1
12.5
UNITS
µs
µs
µs
µs
mA
ms
---
years
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5µs
after VPUP has been applied the parasite capacitance will not affect normal communications.
Guaranteed by design, simulation only. Not production tested.
VTL, VTH, and VHY are a function of the internal supply voltage.
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low.
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
Applies to a single DS2431 attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of VPUP and the time at which the voltage is 20% of VPUP.
ε represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH.
δ represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus
master.
Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming interval
should be such that the voltage at I/O is greater than or equal to Vpup(min). If Vpup in the system is close to Vpup(min) then a
low impedance bypass of Rpup which can be activated during programming may need to be added.
Interval begins tWiLMIN after the leading negative edge on IO for the last timeslot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from IPROG to IL.
PARAMETER
tSLOT (incl. tREC)
tRSTL
tPDH
tPDL
tW0L
LEGACY VALUES
STANDARD SPEED OVERDRIVE SPEED
MIN
MAX
MIN
MAX
61µs
(undef.)
7µs
(undef.)
480µs
(undef.)
48µs
80µs
15µs
60µs
2µs
6µs
60µs
240µs
8µs
24µs
60µs
120µs
6µs
16µs
DS2431 VALUES
STANDARD SPEED OVERDRIVE SPEED
MIN
MAX
MIN
MAX
65µs1)
(undef.)
9µs
(undef.)
504µs
640µs
53µs
80µs
15µs
63µs
2µs
7µs
60µs
240µs
8µs
26µs
60µs
120µs
7µs
16µs
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
PIN DESCRIPTION
NAME
FUNCTION
I/O
1-Wire Bus Interface. Open drain, requires external pullup resistor.
GND
Ground Reference
N.C.
Not Connected
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