DM74S51 データシートの表示（PDF） - Fairchild Semiconductor
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DM74S51 Datasheet PDF : 3 Pages
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August 1986
Revised April 2000
DM74S51
Dual 2-Wide 2-Input AND-OR-INVERT Gate
General Description
This device contains two independent combinations of
gates each of which performs the logic AND-OR-INVERT
function.
Ordering Code:
Order Number Package Number
Package Description
DM74S51N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Y = AB + CD
Inputs
A
B
C
D
H
H
X
X
X
X
H
H
All other
combinations
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
Output
Y
L
L
H
© 2000 Fairchild Semiconductor Corporation DS006454
www.fairchildsemi.com
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