DM74S280MX データシートの表示（PDF） - Fairchild Semiconductor

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DM74S280MX

9-Bit Parity Generator/Checker

Fairchild Semiconductor 

Logic Diagram

Typical Applications

Three DM74S280’s can be used to implement a 25-line

parity generator/checker. This arrangement will provide

parity in typically 25 ns. (See Figure 1.)

Longer word lengths can be implemented by cascading

DM74S280’s. As shown in Figure 2, parity can be gener-

ated for word lengths up to 81 bits in typically 25 ns.

FIGURE 1. 25-Line Parity/Generator Checker

FIGURE 2. 81-Line Parity/Generator Checker

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