CY7C4275V-15(2001) データシートの表示（PDF） - Cypress Semiconductor
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CY7C4275V-15 Datasheet PDF : 20 Pages
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CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Depth Expansion Configuration
(with Programmable Flags)
The CY7C4255/65/75/85V can easily be adapted to applica-
tions requiring more than 8K/16K/32K/64K words of buffering.
Figure 2 shows Depth Expansion using three CY7C4255/65/
75/85Vs. Maximum depth is limited only by signal loading. Fol-
low these steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must
be tied to the Write Expansion In (WXI) pin of the next
device.
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expan-
sion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
VCC
FL
FF
EF
PAF
PAE
WXI RXI
DATAIN (D)
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
VCC
FL
FF
EF
PAF
PAE
WXI RXI
DATA OUT (Q)
LOAD (LD)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
RESET (RS)
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
FF
PAF
FF
EF
PAFWXI RXIPAE
FIRST LOAD (FL)
EF
PAE
Figure 2. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
4275V–25
Document #: 38-06012 Rev. **
Page 17 of 20
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