CY7C4275V-15(2001) データシートの表示（PDF） - Cypress Semiconductor

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CY7C4275V-15
(Rev.:2001)

32K/64Kx18 Low Voltage Deep Sync FIFOs

Cypress Semiconductor 

CY7C4255V/CY7C4265V

CY7C4275V/CY7C4285V

Switching Waveforms (continued)

Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))

WCLK

tCLKH

WEN

PAF

RCLK

REN

tCLKL

tENS tENH

FULL – M + 1 WORDS

IN FIFO

Note 27

tPAF

FULL– M WORDS

IN FIFO [25]

tSKEW3[28]

tENS

tENS tENH

tPAF synch

4275V–18

Write Programmable Registers

tCLKH

tCLK

tCLKL

WCLK

LD

tENS

tENH

WEN

tENS

tDS

tDH

PAE OFFSET

D0 –D17

PAE OFFSET

PAF OFFSET

D0 – D11

4275V–19

Notes:

27. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.

28. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge

of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.

Document #: 38-06012 Rev. **

Page 12 of 20

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