CY7C1355C-100BGC データシートの表示（PDF） - Cypress Semiconductor

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CY7C1355C-100BGC

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

1

Logic Block Diagram – CY7C1355C (256K x 36)

A0, A1, A

MODE

CLK

C

CE

CEN

ADDRESS

REGISTER

A1

A0

D1

D0

ADV/LD

C

WRITE ADDRESS

REGISTER

Q1

Q0

A1'

A0'

BURST

LOGIC

ADV/LD

BWA

BWB

BWC

BWD

WE

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

S

E

N

MEMORY

S

WRITE

ARRAY

E

DRIVERS

A

M

P

S

OE

CE1

READ LOGIC

CE2

CE3

ZZ

SLEEP

CONTROL

2

Logic Block Diagram – CY7C1357C (512K x 18)

A0, A1, A

MODE

CLK

C

CE

CEN

ADDRESS

REGISTER

A1

A0

D1

D0

ADV/LD

C

WRITE ADDRESS

REGISTER

Q1

Q0

A1'

A0'

BURST

LOGIC

INPUT E

REGISTER

ADV/LD

BWA

BWB

WE

OE

CE1

CE2

CE3

ZZ

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

S

E

N

MEMORY

S

WRITE

ARRAY

E

DRIVERS

A

M

P

S

INPUT E

REGISTER

CY7C1355C

CY7C1357C

O

U

T

D

P

A

U

T

T

A

B

S

U

T

F

E

F

E

E

R

R

I

S

N

E

G

DQs

DQPA

DQPB

DQPC

DQPD

O

U

T

D

P

A

U

T

T

A

B

S

U

DQs

T

F

E

F

E

E

DQPA

DQPB

R

R

I

S

N

E

G

Document #: 38-05539 Rev. *E

Page 2 of 28

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