CY7C1348G データシートの表示（PDF） - Cypress Semiconductor

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CY7C1348G

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Cypress Semiconductor 

CY7C1348G

Document History Page

Document Title: CY7C1348G 4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Document Number: 38-05608

REV.

Orig. of

ECN NO. Issue Date Change

Description of Change

**

238089 See ECN RKF New data sheet

*A

288909 See ECN

VBL Changed part numbers to PB-Free part numbers in Ordering Info section

*B

332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP Package as

per JEDEC standards and updated the Pin Definitions accordingly

Modified VOL, VOH test conditions

Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal

Resistance table

Updated the Ordering Information by shading and unshading MPNs as per

availability

*C

419264 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Modified test condition from VIH < VDD to VIH < VDD

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table

Replaced Package Name column with Package Diagram in the Ordering

Information table

Replaced Package Diagram of 51-85050 from *A to *B

Updated the Ordering Information

*D

480368 See ECN VKN Converted from Preliminary to Final.

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

Updated the Ordering Information table.

Document #: 38-05608 Rev. *D

Page 16 of 16

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