datasheetbank_Logo
データシート検索エンジンとフリーデータシート

CY7C037V-25AC(2004) データシートの表示(PDF) - Cypress Semiconductor

部品番号
コンポーネント説明
メーカー
CY7C037V-25AC
(Rev.:2004)
Cypress
Cypress Semiconductor 
CY7C037V-25AC Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CY7C027V/028V
CY7C037V/038V
Switching Characteristics Over the Operating Range[11](continued)
Parameter
Description
tHD
Data Hold From Write End
tHZWE[14, 15]
R/W LOW to High Z
tLZWE[14 ,15]
R/W HIGH to Low Z
tWDD[41]
Write Pulse to Data Delay
tDDD[41]
Write Data Valid to Read Data Valid
Busy Timing[16]
tBLA
BUSY LOW from Address Match
tBHA
BUSY HIGH from Address Mismatch
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-Up for Priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[18]
BUSY HIGH to Data Valid
Interrupt Timing[16]
tINS
INT Set Time
tINR
INT Reset Time
Semaphore Timing
tSOP
tSWRD
tSPS
tSAA
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
CY7C037V/038V
-15
-20
-25
Min. Max. Min. Max. Min. Max. Unit
0
0
0
ns
10
12
15
ns
3
3
3
ns
30
40
50
ns
25
30
35
ns
15
20
20
ns
15
20
20
ns
15
20
20
ns
15
16
17
ns
5
5
5
ns
0
0
0
ns
13
15
17
ns
15
20
25
ns
15
20
20
ns
15
20
20
ns
10
10
12
ns
5
5
5
ns
5
5
5
ns
15
20
25
ns
Data Retention Mode
Timing
The CY7C027V/028V and CY7037V/038V are designed with
battery backup in mind. Data retention voltage and supply cur-
rent are guaranteed over temperature. The following rules en-
sure data retention:
1. Chip enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the min-
imum operating voltage (3.0 volts).
Data Retention Mode
VCC
3.0V
VCC > 2.0V
3.0V
tRC
CE
VCC to VCC – 0.2V
VIH
Parameter
Test Conditions[19] Max. Unit
ICCDR1
@ VCCDR = 2V
50
µA
16. For information on port-to-port delay through RAM cells from writing port
to reading port, refer to Read Timing with Busy waveform.
17. Test conditions used are Load 1.
18. tBDD is a calculated parameter and is the greater of tWDD–tPWE(actual) or tDDD–tSD
(actual).
19. CE = VCC, Vin = GND to VCC, TA = 25° C. This parameter is guaranteed
but not tested.
Document #: 38-06078 Rev. *A
Page 8 of 18

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]