CY7B992-5JC データシートの表示（PDF） - Cypress Semiconductor

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CY7B992-5JC

Programmable Skew Clock Buffer

Cypress Semiconductor 

SYSTEM

CLOCK

CY7B991

CY7B992

Figure 8. Board-to-Board Clock Distribution

REF

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

L1

L2

LOAD

Z0

LOAD

Z0

L3

L4

Z0

Z0

FB

REF

FS

4F0

4F1

4Q0

4Q1

3F0 3Q0

3F1 3Q1

2F0 2Q0

2F1 2Q1

1F0 1Q0

1F1 1Q1

TEST

LOAD

LOAD

LOAD

Figure 8 shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays

of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire

delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumu-

lates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers

in series.

Document Number: 38-07138 Rev. *B

Page 15 of 19

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