CY22381FSC-TLGT データシートの表示（PDF） - Cypress Semiconductor
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CY22381FSC-TLGT Datasheet PDF : 11 Pages
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CY22381
CY223811
Electrical Characteristics
Parameter
Description
Conditions[1]
Min
IDD
Total power supply current 3.3 V Power supply; 3 outputs at 50 MHz –
3.3 V Power supply; 3 outputs at 166 MHz –
IDDS
Total power supply current in Shutdown active
–
shutdown mode
Switching Characteristics
Parameter
Name
1/t1
Output frequency[3, 5]
t2
Output duty cycle[3, 6]
t3
Rising edge slew rate[3]
t4
Falling edge slew rate[3]
t5
Output three-state timing[3]
t6
Clock jitter[3, 7]
t7
Lock time[3]
Switching Waveforms
Description
Clock output limit,commercial
Clock output limit, industrial
Duty cycle for outputs, defined as t2 t1,
Fout < 100 MHz, divider >= 2, measured
at VDD/2
Duty cycle for outputs, defined as t2 t1,
Fout > 100 MHz or divider = 1, measured
at VDD/2
Output clock rise time, 20% to 80% of VDD
Output clock fall time, 20% to 80% of VDD
Time for output to enter or leave
three-state mode after SHUTDOWN/OE
switches
Peak-to-peak period jitter, CLK outputs
measured at VDD/2
PLL Lock Time from Power up
Min
–
–
45%
40%
0.75
0.75
–
–
–
Figure 2. All Outputs, Duty Cycle and Rise and Fall Time
t1
t2
OUTPUT
t3
t4
Typ
35
70
5
Typ.
–
–
50%
50%
1.4
1.4
150
200
1.0
Figure 3. Output Three-State Timing
OE
t5
t5
ALL
THREE-STATE
OUTPUTS
Notes
4. Guaranteed by design, not 100% tested.
5. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications.
6. Reference Output duty cycle depends on XTALIN duty cycle.
7. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Max
Unit
–
mA
–
mA
20
A
Max
200
166
55%
Unit
MHz
MHz
60%
–
V/ns
–
V/ns
300
ns
–
ps
3
ms
Document #: 38-07012 Rev. *I
Page 6 of 11
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