CY14B101Q1A データシートの表示（PDF） - Cypress Semiconductor

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CY14B101Q1A

1-Mbit (128 K × 8) Serial (SPI) nvSRAM

Cypress Semiconductor 

CY14C101Q

CY14B101Q, CY14E101Q

CS

SCK

SI

SO

Figure 13. Burst Mode Read Instruction Timing

01 2 3 456 7 01 2 3 45 6 7

20 21 22 23 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7

Op-Code

17-bit Address

0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 A16

MSB

A3 A2 A1 A0

LSB

Data Byte 1

Data Byte N

HI-Z

D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB

MSB

LSB

Figure 14. Fast Read Instruction Timing

CS

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7

SCK

Op-Code

17-bit Address

Dummy Byte

SI

0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 A16 A3 A2 A1 A0 X X X X X X X X

MSB

LSB

SO

HI-Z

D7 D6 D5 D4 D3 D2 D1 D0

MSB

Data

LSB

Figure 15. Write Instruction Timing

CS

SCK

0 1 2 34 5 67 0 1 23 4 56 7

20 21 22 23 0 1 2 3 4 5 6 7

Op-Code

17-bit Address

SI

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 A16 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB MSB

Data

LSB

SO

HI-Z

Figure 16. Burst Mode Write Instruction Timing

CS

SCK

SI

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 20 21 22 23 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7

Data Byte 1

Data Byte N

Op-Code

17-bit Address

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 A16 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB MSB

LSB

SO

HI-Z

Document #: 001-54393 Rev. *F

Page 14 of 34

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