CY14B101P-SFXI(2012) データシートの表示（PDF） - Cypress Semiconductor

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CY14B101P-SFXI
(Rev.:2012)

1-Mbit (128 K × 8) Serial SPI nvSRAM with Real Time Clock

Cypress Semiconductor 

CY14B101P

flag and the hardware interrupt are both cleared when user reads

the flags register.

.

Figure 21. Watchdog Timer Block Diagram

Oscillator

32,768 KHz

Clock

Divider

32 Hz

Counter

1 Hz

Zero

Compare

WDF

WDS

WDW

DQ

Q

write to

Watchdog

Register

Load

Register

Watchdog

Register

Power Monitor

The CY14B101P provides a power management scheme with

power fail interrupt capability. It also controls the internal switch

to backup power for the clock and protects the memory from low

VCC access. The power monitor is based on an internal bandgap

reference circuit that compares the VCC voltage to VSWITCH

threshold.

As described in the section AutoStore Operation on page 4,

when VSWITCH is reached as VCC decays from power loss, a data

STORE operation is initiated from SRAM to the nonvolatile

elements, securing the last SRAM data state. Power is also

switched from VCC to the backup supply (battery or capacitor) to

operate the RTC oscillator.

When operating from the backup source, read and write

operations to nvSRAM are inhibited and the RTC functions are

not available to the user. The RTC clock continues to operate in

the background. The updated RTC time keeping registers data

are available to the user after VCC is restored to the device (see

AutoStore or Power-Up RECALL on page 28).

Interrupts

The CY14B101P has a flags register, interrupt register, and

Interrupt logic that can signal interrupt to the microcontroller.

There are three potential sources for interrupt: watchdog timer,

power monitor, and alarm timer. Each of these can be individually

enabled to drive the INT pin by appropriate setting in the interrupt

register (0x06). In addition, each has an associated flag bit in the

flags register (0x00) that the host processor uses to determine

the cause of the interrupt. The INT pin driver has two bits that

specify its behavior when an interrupt occurs.

An interrupt is raised only if both a flag is raised by one of the

three sources and the respective interrupt enable bit in interrupts

register is enabled (set to ‘1’). After an interrupt source is active,

two programmable bits, H/L and P/L, determine the behavior of

the output pin driver on INT pin. These two bits are located in the

interrupt register and can be used to drive level or pulse mode

output from the INT pin. In pulse mode, the pulse width is

internally fixed at approximately 200 ms. This mode is intended

to reset a host microcontroller. In the level mode, the pin goes to

its active polarity until the flags register is read by the user. This

mode is used as an interrupt to a host microcontroller. The

control bits are summarized in the following section.

Interrupts are only generated while working on normal power and

are not triggered when system is running in backup power mode.

Note CY14B101P generates valid interrupts only after the

Power-Up RECALL sequence is completed. All events on INT

pin must be ignored for tFA duration after power-up.

Interrupt Register

Watchdog Interrupt Enable (WIE). When set to ‘1’, the

watchdog timer drives the INT pin and an internal flag when a

watchdog time out occurs. When WIE is set to ‘0’, the watchdog

timer only affects the WDF flag in flags register.

Alarm Interrupt Enable (AIE). When set to ‘1’, the alarm match

drives the INT pin and an internal flag. When AIE is set to ‘0’, the

alarm match only affects the AF flag in flags register.

Power Fail Interrupt Enable (PFE). When set to ‘1’, the power

fail monitor drives the pin and an internal flag. When PFE is set

to ‘0’, the power fail monitor only affects the PF flag in flags

register.

High/Low (H/L). When set to a ‘1’, the INT pin is active HIGH

and the driver mode is push pull. The INT pin drives HIGH only

when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin

is active LOW and the drive mode is open drain. The INT pin

must be pulled up to VCC by a 10 k resistor while using the

interrupt in active LOW mode.

Pulse/Level (P/L). When set to a ‘1’ and an interrupt occurs, the

INT pin is driven for approximately 200 ms. When P/L is set to a

‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until

the flags register is read.

When an enabled interrupt source activates the INT pin, an

external host reads the flags registers to determine the cause.

Remember that all flags are cleared when the register is read. If

the INT pin is programmed for Level mode, then the condition

clears and the INT pin returns to its inactive state. If the pin is

programmed for pulse mode, then reading the flag also clears

the flag and the pin. The pulse does not complete its specified

duration if the flags register is read. If the INT pin is used as a

host reset, the flags register is not read during a reset.

Flags Register

The flags register has three flag bits: WDF, AF, and PF, which

can be used to generate an interrupt. These flags are set by the

watchdog timeout, alarm match, or power fail monitor

respectively. The processor can either poll this register or enable

interrupts to be informed when a flag is set. These flags are

automatically reset when the register is read. The flags register

is automatically loaded with the value 0x00 on power-up (except

for the OSCF bit. See Stopping and Starting the Oscillator on

page 16).

Document Number: 001-44109 Rev. *M

Page 18 of 36

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