CY14B101LA-SZ20XC データシートの表示（PDF） - Cypress Semiconductor
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CY14B101LA-SZ20XC Datasheet PDF : 24 Pages
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PRELIMINARY
CY14B101LA, CY14B101NA
AutoStore/Power Up RECALL
Parameters
Description
tHRECALL [27] Power Up RECALL Duration
tSTORE [23] STORE Cycle Duration
tDELAY [24] Time Allowed to Complete SRAM Write Cycle
VSWITCH Low Voltage Trigger Level
tVCCRISE[13] VCC Rise Time
VHDIS[13]
tLZHSB[13]
tHHHD[13]
HSB Output Disable Voltage
HSB To Output Active Time
HSB High Active Time
Switching Waveforms
20 ns
Min
Max
20
8
20
2.65
150
1.9
5
500
25 ns
Min
Max
20
8
25
2.65
150
1.9
5
500
Figure 11. AutoStore or Power Up RECALL[27]
VCC
VSWITCH
VHDIS
45 ns
Unit
Min
Max
20
ms
8
ms
25
ns
2.65
V
150
µs
1.9
V
5
µs
500
ns
HSB OUT
AutoStore
POWER-
UP
RECALL
Read & Write
Inhibited
(RWI)
VVCCRISE
tHHHD
Note23
tSTORE
tLZHSB
tHRECALL
tDELAY
tHHHD
23
Note
tSTORE
26
Note
tDELAY
tLZHSB
tHRECALL
POWER-UP
RECALL
Read & Write
BROWN POWER-UP
OUT
RECALL
AutoStore
Read & Write
POWER
DOWN
AutoStore
Notes
22. tHRECALL starts from the time VCC rises above VSWITCH.
23. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
24. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
25. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
26. HSB pin is driven high to VCC only by internal 100 kΩ resistor, HSB driver is disabled.
Document #: 001-42879 Rev. *C
Page 13 of 24
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