CS5466(2004) データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CS5466
(Rev.:2004)

Low Cost Power/Energy IC with Pulse Output

Cirrus Logic 

CS5466

SWITCHING CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.

Parameter

Symbol Min

Typ

Max Unit

Rise Times

(Note 10)

Any Digital Input trise

Any Digital Output

-

-

1.0

µs

-

50

-

ns

Fall Times

(Note 10)

Any Digital Input tfall

Any Digital Output

-

-

1.0

µs

-

50

-

ns

Start-up

Oscillator Start-Up Time

XTAL = 4.096 MHz (Note 11) tost

-

60

-

ms

E1 and E2 Timing (Note 12 and 13)

Period

t1

500

-

ms

Pulse Width

t2

250

-

-

ms

Rising Edge to Falling Edge

t3

250

ms

E1 Falling Edge to E2 Falling Edge

t4

250

-

ms

FOUT Timing (Note 12 and 13)

Period

t5

0.10 1 / fFOUT

ms

Pulse Width

(Note 14)

t6

-

0.5*t5

90

ms

FOUT low

t7

-

0.5*t5

-

ms

Notes: 10.

11.

12.

13.

14.

Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external

clock source.

Pulse output timing is specified at MCLK = 4.096 MHz. Current and voltage signals are at unity power factor. Refer

to Section 5.3 for more information on pulse output pins.

Timing is proportional to the frequency of MCLK.

When FREQ2 = 0, FREQ1=1 and FREQ0=1, FOUT will have a typical pulse width of 20 µs at MCLK = 4.096 MHz.

t1

E1

t2

t3

t4

E2

t2

t1

t3

t5

FOUT

t6

t7

Figure 1. Timing Diagram for E1, E2 and FOUT

8

Share Link: