CS5466(2004) データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CS5466
(Rev.:2004)

Low Cost Power/Energy IC with Pulse Output

Cirrus Logic 

CS5466

DIGITAL CHARACTERISTICS (Note 6)

• Min / Max characteristics and specifications are guaranteed over all Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• MCLK = 4.096 MHz

Parameter

Symbol

Master Clock Characteristics

Master Clock Frequency

Internal Gate Oscillator MCLK

Master Clock Duty Cycle

CPUCLK Duty Cycle

(Note 7 and 8)

Filter Characteristics

High Pass Filter Corner Frequency

-3 dB

Input/Output Characteristics

High-Level Input Voltage

VIH

XIN

RESET

Low-Level Input Voltage (VD = 5 V)

VIL

XIN

RESET

Low-Level Input Voltage (VD = 3.3 V)

VIL

XIN

RESET

High-Level Output Voltage (except XOUT)

Iout = +5 mA VOH

Low-Level Output Voltage (except XOUT)

Iout = -5 mA VOL

Input Leakage Current

Iin

Digital Output Pin Capacitance

Cout

Drive Current FOUT, E1, E2, NEG

(Note 9) IDR

Min

Typ

3

4.096

40

-

40

-

0.125

(VD+) - 0.5 -

0.8 VD+

-

-

-

-

-

-

-

-

-

(VD+) - 1.0 -

-

-

-

±1

-

5

90

Max

5

60

60

-

-

-

1.5

0.2 VD+

0.3

0.2 VD+

-

0.4

±10

-

Unit

MHz

%

%

Hz

V

V

V

V

V

V

V

V

µA

pF

mA

Notes: 6. All measurements performed under static conditions.

7. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.

8. The frequency of CPUCLK is equal to MCLK.

9. VOL and VOH are not specified under this condition.

7

Share Link: