VN16117
Preliminary
TX_CLK
TX<9:0>
1.4 V
DATA
DATA
DATA
tSETUP
tHOLD
DATA
DATA
DATA
2.0 V
0.8 V
Figure 3. Transmitter Section Timing.
DATA BYTE A
DATA BYTE B
DOUT± T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5
TX<9:0>
t_TXLAT
DATA BYTE B
DATA BYTE C
TX_CLK
1.4 V
Figure 4. Transmitter Latency
2001-08-09
Page 9
MDSN-0002-02
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