BD6761FV-E2 データシートの表示（PDF） - ROHM Semiconductor
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BD6761FV-E2 Datasheet PDF : 23 Pages
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BD6761FS,BD6762FV
Technical Note
Design method
⑫Phase compensation capacitor (BD6761FS)
Phase compensation is performed in the output of the CS
amplifier. The capacitance value should be selected according
to the servo constant, and proper motor operation should be
confirmed. When the capacitance is large, the I/O response
becomes bad. When it is small, the output becomes easy to
oscillate.
⑬VCC pin
Set up the capacitance for the stabilization and noise reduction
on the power line.
⑭Charge pump filter(BD6761FS)
Filter composed of C3, C4 and R3 smoothes the current pulses
output from the CPOUT pin and converts it to DC.
This impedance Z is shown by the following equation.
C4
S+ω2
Z = R3× C3+C4 ×
S
1+
S
ω1
When the pole frequency is set to fP1 and fP2, they are:
fP1=ω1/2π=1/2π(C3//C4)R3
fP2=ω2/2π=1/2πC4R3
⑮Output FET gate voltage stabilization resistor
When the noise is generated at the time of external MOSFET
on/off due to the rise and fall speed of the IC output, insert the
resistor between the IC output and external MOSFET gate.
Design example
A value of 0.001μF to 0.1μF is recommended.
A value of 0.001μF is appropriate for BA6680FS.
A value of 0.1μF is appropriate for BD6761FS.
A value of value 1μF to 10μF is recommended.
A value of 10μF is appropriate.
Recommended value
C3: 0.01μF to 0.1μF; a value of 0.01μF is appropriate.
C4: 0.033μF to 0.33μF; a value of 0.1μF is appropriate.
R3 : 30kΩ to 300kΩ; a value of 100kΩ is appropriate.
Establish R so that the simultaneous on prevention time
is not exceeded as shown in 7). Output simultaneous on
prevention circuit in P.17/24 Operating Explanation.
A value of R = 0Ω is appropriate.
⑯Peak hold setting capacitor (BD6761FS)
Charges the peak hold on the voltage at the current detection
pin CL.
⑰Motor locking detection time setting capacitor (BD6762FV)
Motor locking detection time TLP is determined by the capacitor
C7 which is connected to the LP pin and the count number CLP
(Preset value: 96) of the internal counter. The TLP is shown by
the following equation.
TLP=2×105×C7×96
⑱Integration amplifier constant setting (BD6762FV)
Speed discriminator side current value ID is shown by|ID|=2.5/R4
and the PLL side current value IP is shown by|IP|=2.5/R5.
Therefore, the current IIN which flows in the integration AMP
input pin INTIN is shown by IIN=ID+IP.
The larger the IIN is, the higher the integration amplifier gain
becomes.
Gains of the speed discriminator and PLL can be set by
adjusting R4 and R5.
Gain G is shown by the following equation.
R6
G = R4 // R5 ×
C6
C5+C6 ×
S+ω2
S
1+
S
ω1
A value of 0.33μF is appropriate.
A value of 0.22μF is appropriate.
Recommended value
R4: 10kΩ to 40kΩ; a value of 20 kΩ is appropriate.
R5: 300kΩ to 3MΩ; a value of 1 MΩ is appropriate.
R6: 100kΩ to 500kΩ; a value of 220 kΩ is appropriate.
C5: 0.01μF to 0.1μF; a value of 0.047μF is appropriate.
C6: 0.033μF to 1.0μF; a value of 0.47μF is appropriate.
When the pole frequency is set to fP1 and fP2, they are:
fP1=ω1/2π=1/2π(C5//C6)×R6
fP2=ω2/2π=1/2πC6R6
⑲LPF external constant (BD6762FV)
Filter composed of C8, C9 and R7 smoothes the current pulses
output from the LPF pin and converts it to DC.
This impedance Z is shown by the following equation.
Recommended value
C8: 0.1μF to 0.6μF; a value of 0.33μF is appropriate.
C9: 0.1μF to 0.6μF; a value of 0.33μF is appropriate.
R7: 0.5kΩ to 10kΩ; a value of 2kΩ is appropriate.
Z = R7×
C9
C8+C9 ×
S+ω2
S
1+
S
ω1
When the pole frequency is set to fP1 and fP2, they are:
fP1=ω1/2π=1/2π(C8//C9)R7 fP2=ω2/2π=1/2πC9R7
※Setting values in these materials are only for reference. Actual set may change its characteristics due to the boards layout, wiring and components type to use.
Please perform the sufficient verification using the actual product for the field operation.
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19/22
2010.06 - Rev.A
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