
4.0 System Architecture and
Reference Design
4.1 AU6390 Block Diagram
Figure 4.1 AU6390 Block Diagram
USB
USB
XCVR
SIE
RAM
ATA Control FIFO
ATA
Upstream
Port
2.5 V
Processor
ROM
Arbitrator
2.5V
Voltage
Regulator
/Power Switch
3.3V
12MHz
XTAL
AU6390 USB2.0 to ATA/ATAPI Bridge Controller V0.9W
Preliminary Release_ confidential
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