AT45DB321C-TI データシートの表示（PDF） - Atmel Corporation
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AT45DB321C-TI Datasheet PDF : 40 Pages
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Table 9-1. Read Commands
Command
SCK Mode
Opcode
RapidS Mode 0 or 3
E8H
Continuous Array Read
Inactive Clock Polarity Low or High
68H
Main Memory Page Read
RapidS Mode 0 or 3
Inactive Clock Polarity Low or High
D2H
52H
Buffer 1 Read
RapidS Mode 0 or 3
Inactive Clock Polarity Low or High
D4H
54H
Buffer 2 Read
RapidS Mode 0 or 3
Inactive Clock Polarity Low or High
D6H
56H
Status Register Read
RapidS Mode 0 or 3
Inactive Clock Polarity Low or High
D7H
57H
Manufacturer and Device ID
RapidS Mode 0 or 3
9FH
Note: 1. Legacy Opcodes 52H, 54H, 56H, 57H, and 68H are still supported for reasons of backward compatibility only and are not
recommended for new designs. The inactive clock polarity high or low modes will not be supported in the future products.
Table 9-2. Program and Erase Commands
Command
Buffer 1 Write
Buffer 2 Write
Buffer 1 to Main Memory Page Program with Built-in Erase
Buffer 2 to Main Memory Page Program with Built-in Erase
Buffer 1 to Main Memory Page Program without Built-in Erase
Buffer 2 to Main Memory Page Program without Built-in Erase
Page Erase
Block Erase
Main Memory Page Program Through Buffer 1
Main Memory Page Program Through Buffer 2
SCK Mode
Mode 0, Mode 3
Mode 0, Mode 3
Mode 0, Mode 3
Mode 0, Mode 3
Mode 0, Mode 3
Mode 0, Mode 3
Mode 0, Mode 3
Mode 0, Mode 3
Mode 0, Mode 3
Mode 0, Mode 3
Opcode
84H
87H
83H
86H
88H
89H
81H
50H
82H
85H
18 AT45DB321C
3387M–DFLASH–2/08
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