AT45DB321C-TI データシートの表示（PDF） - Atmel Corporation
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AT45DB321C-TI Datasheet PDF : 40 Pages
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AT45DB321C
8. Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device
will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a
high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode
3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive
clock state. After power is applied and VCC is at the minimum datasheet value, the system
should wait 20 ms before an operational mode (DataFlash) is started.
9. System Considerations
The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip select
CS pins. These signals must rise and fall monotonically and be free from noise. Excessive noise
or ringing on these pins can be misinterpreted as multiple edges and cause improper operation
of the device. The PC board traces must be kept to a minimum distance or appropriately termi-
nated to ensure proper operation. If necessary, decoupling capacitors can be added on these
pins to provide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important.
A key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak current for DataFlash occur during the programming and erase operation.
The regulator needs to supply this peak current requirement. An under specified regulator can
cause current starvation. Besides increasing system noise, current starvation during program-
ming or erase can lead to improper operation and possible data corruption.
For applications that require random modifications of data within a sector, please refer to “Auto
Page Rewrite” on page 8.
Atmel C generation DataFlash utilizes a sophisticated adaptive algorithm during erase and pro-
gramming to maximize the endurance over the life of the device. The algorithm uses a
verification mechanism to check if the memory cells have been erased or programmed success-
fully. If the memory cells were not erased or programmed completely, the algorithm erases or
programs the memory cells again. The process will continue until the device is erased or pro-
grammed successfully.
In order to optimize the erase and programming time, fixed timing should not be used.
Instead, the RDY/BUSY bit of the status register or the RDY/BUSY pin should be
monitored.
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3387M–DFLASH–2/08
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