Table 6-2. Sector Erase Addressing
PA11/ PA10/
A20 A19
0
0
0
0
0
0
0
0
•
•
•
•
•
•
1
1
1
1
1
1
1
1
PA9/
A18
0
0
0
1
•
•
•
0
0
1
1
PA8/
A17
0
0
1
0
•
•
•
0
1
0
1
PA7/
A16
0
0
X
X
•
•
•
X
X
X
X
PA6/
A15
0
0
X
X
•
•
•
X
X
X
X
PA5/
A14
0
0
X
X
•
•
•
X
X
X
X
PA4/
A13
0
0
X
X
•
•
•
X
X
X
X
PA3/
A12
0
1
X
X
•
•
•
X
X
X
X
PA2/
A11
X
X
X
X
•
•
•
X
X
X
X
PA1/
A10
X
X
X
X
•
•
•
X
X
X
X
PA0/
A9
X
X
X
X
•
•
•
X
X
X
X
Sector
0a
0b
1
2
•
•
•
12
13
14
15
6.9 Chip Erase
The entire main memory can be erased at one time by using the Chip Erase command.
To execute the Chip Erase command, a 4-byte command sequence of C7h, 94h, 80h, and 9Ah must be clocked into the
device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. After the last bit of the opcode sequence has been clocked in, the CS pin
must be deasserted to start the erase process. The erase operation is internally self-timed and should take place in a
time of tCE. During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.
The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will
remain unchanged. Only those sectors that are not protected or locked down will be erased.
The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle
completes.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to erase or
program properly. If an erase programming error arises, it will be indicated by the EPE bit in the Status Register.
Table 6-3. Chip Erase Command
Command
Chip Erase
Byte 1
C7h
Byte 2
94h
Byte 3
80h
Byte 4
9Ah
Figure 6-1. Chip Erase
CS
C7h
94h
80h
9Ah
Each transition represents eight bits
Atmel AT45DB161E [PRELIMINARY DATASHEET] 14
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