AT45DB081B(2001) データシートの表示（PDF） - Atmel Corporation

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AT45DB081B
(Rev.:2001)

8-megabit 2.5-volt Only or 2.7-volt Only DataFlash®

Atmel Corporation 

AT45DB081B

Reset Timing (Inactive Clock Polarity Low Shown)

CS

SCK

RESET

SO

HIGH IMPEDANCE

tREC

tRST

tCSS

HIGH IMPEDANCE

SI

Note: The CS signal should be in the high state before the RESET signal is deasserted.

Command Sequence for Read/Write Operations (except Status Register Read)

SI

CMD 8 bits 8 bits 8 bits

MSB

r r r XXXXX XXXX XXXX XXXX XXXX

LSB

Reserved for

larger densities

Page Address

(PA11-PA0)

Byte/Buffer Address

(BA8-BA0/BFA8-BFA0)

Notes: 1. “r” designates bits reserved for larger densities.

2. It is recommended that “r” be a logical “0” for densities of 8M bits or smaller.

3. For densities larger than 8M bits, the “r” bits become the most significant Page Address bit for the appropriate density.

15

2225C–12/01

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