AT45D081 データシートの表示（PDF） - Atmel Corporation

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AT45D081

8-Megabit 5-volt Only Serial DataFlash™

Atmel Corporation 

AT45D081

AC Waveforms

Two different timing diagrams are shown below. Waveform

1 shows the SCK signal being low when CS makes a high-

to-low transition, and Waveform 2 shows the SCK signal

being high when CS makes a high-to-low transition. Both

wavforms show valid timing diagrams. The setup and hold

times for the SI signal are referenced to the low-to-high

transition on the SCK signal.

Waveform 1 shows timing that is also compatible with SPI

Mode 0, and Waveform 2 shows timing that is compatible

with SPI Mode 3.

Waveform 1 – Inactive Clock Polarity Low

CS

tCSS

tWH tWL

tCSH

SCK

tV

HIGH IMPEDANCE

SO

tHO

VALID OUT

tSU

tH

SI

VALID IN

tCS

tDIS

HIGH IMPEDANCE

Waveform 2 – Inactive Clock Polarity High

CS

SCK

SO

SI

tCSS tWL tWH

tV

HIGH Z

tSU

tHO

VALID OUT

tH

VALID IN

tCSH

tCS

tDIS

HIGH IMPEDANCE

Command Sequence for Read/Write Operations (Except Status Register Read)

SI

CMD 8 bits 8 bits 8 bits

MSB

r r r X XXXX XXXX XXXX XXXX XXXX

LSB

Reserved for

larger densities

Page Address

(PA11-PA0)

Byte/Buffer Address

(BA8-BA0/BFA8-BFA0)

Notes: 1. “r” designates bits reserved for larger densities.

2. It is recommended that “r” be a logical “0” for densities of 8M bit or smaller.

3. For densities larger than 8M bit, the “r” bits become the most significant Page Address bit for the appropriate density.

7

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