LTC1289CCSW(RevB) データシートの表示（PDF） - Linear Technology

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LTC1289CCSW
(Rev.:RevB)

3 Volt Single Chip 12-Bit Data Acquisition System

Linear Technology 

LTC1289

DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which

apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER

CONDITIONS

LTC1289B

LTC1289C

MIN TYP MAX

UNITS

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IIH

High Level Input Current

IIL

Low Level Input Current

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

IOZ

High Z Output Leakage

ISOURCE

ISINK

ICC

Output Source Current

Output Sink Current

Positive Supply Current

IREF

Reference Current

I–

Negative Supply Current

VCC = 3.6V

●

2.1

V

VCC = 3.0V

●

0.45

V

VIN = VCC

●

2.5

µA

VIN = 0V

●

– 2.5

µA

VCC = 3.0V

IO = 20µA

IO = 400µA

V

●

2.90

2.7 2.85

VCC = 3.0V

IO = 20µA

IO = 400µA

V

●

0.05

0.10 0.3

VOUT = VCC, CS High

●

VOUT = 0V, CS High

●

3

µA

–3

µA

VOUT = 0V

– 10

mA

VOUT = VCC

9

mA

CS High

●

CS High, Power Shutdown, ACLK Off

●

1.5 5

mA

1.0 10

µA

VREF = 2.5V

●

10 50

µA

CS High

●

1

50

µA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with DGND, AGND

and REF –wired together (unless otherwise noted).

Note 3: VCC = 3V, VREF+ = 2.5V, VREF– = 0V, V – = 0V for unipolar mode

and – 3V for bipolar mode, ACLK = 2.0MHz unless otherwise specified.

Note 4: These specs apply for both unipolar and bipolar modes. In bipolar

mode, one LSB is equal to the bipolar input span (2VREF) divided by 4096.

For example, when VREF = 2.5V, 1LSB(bipolar) = 2(2.5)/4096 = 1.22mV.

V – = – 2.7V for bipolar mode.

Note 5: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 6: Recommended operating conditions.

Note 7: Two on-chip diodes are tied to each analog input which will

conduct for analog voltages one diode drop below GND or one diode drop

above VCC. Be careful during testing at low VCC levels, as high level analog

inputs can cause this input diode to conduct, especially at elevated

temperature, and cause errors for inputs near full scale. This spec allows

50mV forward bias of either diode. This means that as long as the analog

input does not exceed the supply voltage by more than 50mV, the output

code will be correct.

Note 8: Channel leakage current is measured after the channel selection.

Note 9: To minimize errors caused by noise at the chip select input, the

internal circuitry waits for two ACLK falling edges after a chip select falling

edge is detected before responding to control input signals. Therefore, no

attempt should be made to clock an address in or data out until the

minimum chip select set-up time has elasped. See Typical Peformance

Characteristics curves for additional information (tsuCS vs VCC).

Note 10: Increased leakage currents at elevated temperatures cause the

S/H to droop, therefore it's recommended that fACLK ≥ 125kHz at 85°C and

fACLK ≥ 15kHz at 25°C.

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