MT28C3214P2FL-10T データシートの表示（PDF） - Micron Technology

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MT28C3214P2FL-10T

FLASH AND SRAM COMBO MEMORY

Micron Technology 

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

GENERAL DESCRIPTION

The MT28C3214P2FL and MT28C3214P2NFL com-

bination Flash and SRAM memory devices provide a

compact, low-power solution for systems where PCB

real estate is at a premium. The dual-bank Flash is a

high-performance, high-density, nonvolatile memory

device with a revolutionary architecture that can sig-

nificantly improve system performance.

This new architecture features:

• A two-memory-bank configuration supporting

dual-bank burst operation;

• A high-performance bus interface providing a fast

page data transfer; and

• A conventional asynchronous bus interface.

The device also provides soft protection for blocks

by configuring soft protection registers with dedicated

command sequences. For security purposes, dual 64-

bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state

machine (WSM). The WSM simplifies these operations

and relieves the system processor of secondary tasks.

An on-chip status register, one for each bank, can be

used to monitor the WSM status to determine the

progress of a PROGRAM/ERASE command.

The erase/program suspend functionality allows

compatibility with existing EEPROM emulation soft-

ware packages.

The device takes advantage of a dedicated power

source for the Flash device (F_VCC) and a dedicated

power source for the SRAM device (S_VCC), both at

1.65V–1.95V or 1.80V–2.20V for optimized power con-

sumption and improved noise immunity. The

MT28C3214P2FL and MT28C3214P2NFL devices sup-

port two VPP voltage ranges, VPP1 and VPP2. VPP1 is an

in-circuit voltage of 0.9V–2.2V (MT28C3214P2FL) or

0.0V–2.2V (MT28C3214P2NFL). VPP2 is the production

compatibility voltage of 12V ±5%. The 12V ±5% VPP2 is

supported for a maximum of 100 cycles and 10 cumula-

tive hours. See Table 1.

The MT28C3214P2FL and MT28C3214P2NFL de-

vices contain an asynchronous 4Mb SRAM organized

as 256K-words by 16 bits. These devices are fabricated

using an advanced CMOS process and high-speed/

ultra-low-power circuit technology.

The MT28C3214P2FL and MT28C3214P2NFL de-

vices are packaged in a 66-ball FBGA package with

0.80mm pitch.

DEVICE MARKING

Due to the size of the package, Micron’s standard

part number is not printed on the top of each device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross referenced to Micron part num-

bers in Table 2.

ARCHITECTURE AND MEMORY

ORGANIZATION

The Flash memory device contains two separate

memory banks (bank a and bank b) for simultaneous

READ and WRITE operations. Bank a is 4Mb deep and

contains 8 x 4K-word parameter blocks and seven 32K-

word blocks. Bank b is 28Mb deep, is equally sectored,

and contains fifty-six 32K-word blocks.

Figures 2 and 3 show the top and bottom memory

organizations.

Table 1

VPP Voltage Ranges

DEVICE

MT28C3214P2FL

MT28C3214P2NFL

VOLTAGE RANGE

VPP1

VPP2

0.9V–2.2V 11.4V–12.6V

0.0V–2.2V 11.4V–12.6V

Table 2

Cross Reference for Abbreviated Device Marks

PART NUMBER

MT28C3214P2FL-10 BET

MT28C3214P2FL-10 TET

MT28C3214P2FL-11 BET

MT28C3214P2FL-11 TET

MT28C3214P2NFL-11 TET

PRODUCT

MARKING

FW420

FW421

FW437

FW431

FW439

SAMPLE

MARKING

FX420

FX421

FX437

FX431

FX439

MECHANICAL

SAMPLE MARKING

FY420

FY421

FY437

FY431

FY439

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory

MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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